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SOIC_test
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  1. 33
      .gitignore
  2. 382
      SOIC_test.kicad_pcb
  3. 495
      SOIC_test.kicad_pro
  4. 675
      SOIC_test.kicad_sch

33
.gitignore vendored
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*-backups
gerbers/
gcode/
# imported from gitea project kicad gitignore
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
# Format documentation: http://kicad-pcb.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.sch-bak
*.kicad_prl
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
*.lck
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv

382
SOIC_test.kicad_pcb
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(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(aux_axis_origin 45.72 88.9)
(pcbplotparams
(layerselection 0x0001020_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "Net-(J1-Pin_1)")
(net 2 "Net-(J1-Pin_2)")
(net 3 "Net-(J1-Pin_3)")
(net 4 "Net-(J1-Pin_4)")
(net 5 "Net-(J1-Pin_5)")
(net 6 "Net-(J1-Pin_6)")
(net 7 "Net-(J1-Pin_7)")
(net 8 "Net-(J2-Pin_1)")
(net 9 "Net-(J2-Pin_2)")
(net 10 "Net-(J2-Pin_3)")
(net 11 "Net-(J2-Pin_4)")
(net 12 "Net-(J2-Pin_5)")
(net 13 "Net-(J2-Pin_6)")
(net 14 "Net-(J2-Pin_7)")
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(tstamp a186ac2b-c801-4207-8722-e9dad9dc4df6)
(at 55.88 78.74 90)
(descr "Through hole straight pin header, 1x07, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x07 2.54mm single row")
(property "Sheetfile" "power.kicad_sch")
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(property "ki_description" "Generic connector, single row, 01x07, script generated")
(property "ki_keywords" "connector")
(path "/a03862d6-ca62-4c56-af0f-1e4e5e5aacf2")
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(effects (font (size 1 1) (thickness 0.15)))
(tstamp 0e5f1809-6012-4d9e-a598-42e37869f736)
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(pad "1" thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 8 "Net-(J2-Pin_1)") (pinfunction "Pin_1") (pintype "passive") (tstamp fd5fb528-7e4a-45e5-a93d-39bd23b3940b))
(pad "2" thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 9 "Net-(J2-Pin_2)") (pinfunction "Pin_2") (pintype "passive") (tstamp ecf6b91f-7acb-4bb4-8e05-8126ca04a046))
(pad "3" thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 10 "Net-(J2-Pin_3)") (pinfunction "Pin_3") (pintype "passive") (tstamp 8ca4c5f6-a6ef-4ce3-93c7-24c802b08384))
(pad "4" thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 11 "Net-(J2-Pin_4)") (pinfunction "Pin_4") (pintype "passive") (tstamp e89885f1-778a-4e15-b265-8ef3c2e37308))
(pad "5" thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 12 "Net-(J2-Pin_5)") (pinfunction "Pin_5") (pintype "passive") (tstamp 342edf3b-28e4-4c81-b418-da42f400e528))
(pad "6" thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 13 "Net-(J2-Pin_6)") (pinfunction "Pin_6") (pintype "passive") (tstamp 42d82b85-f03b-40c9-91d8-c2aa7a65ecd4))
(pad "7" thru_hole oval (at 0 15.24 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask")
(net 14 "Net-(J2-Pin_7)") (pinfunction "Pin_7") (pintype "passive") (tstamp 8d62b569-45e3-42b6-af1f-a00a252b788f))
(model "${KICAD6_3DMODEL_DIR}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x07_P2.54mm_Vertical.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Connector_PinHeader_2.54mm:PinHeader_1x07_P2.54mm_Vertical" (layer "F.Cu")
(tstamp b7aac320-5b07-42cb-8b67-a2792f8d7658)
(at 55.88 66.04 90)
(descr "Through hole straight pin header, 1x07, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x07 2.54mm single row")
(property "Sheetfile" "power.kicad_sch")
(property "Sheetname" "")
(property "ki_description" "Generic connector, single row, 01x07, script generated")
(property "ki_keywords" "connector")
(path "/d8379b5f-0388-4c95-a46e-af380fa39196")
(attr through_hole)
(fp_text reference "J1" (at 0 -2.33 90) (layer "F.SilkS")
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(tstamp 01954c8d-32ab-45d1-be23-578736c60305)
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(fp_text value "Conn_01x07_Pin" (at 0 17.57 90) (layer "F.Fab")
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(tstamp a9e57871-150b-4af5-a97d-9f1a03d955b9)
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(fp_text user "${REFERENCE}" (at 0 7.62) (layer "F.Fab")
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(net 4 "Net-(J1-Pin_4)") (pinfunction "Pin_4") (pintype "passive") (tstamp e5c85cab-5a52-4d54-844c-951fbe9ed905))
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(net 6 "Net-(J1-Pin_6)") (pinfunction "Pin_6") (pintype "passive") (tstamp 61b5b8e2-d7a4-4494-bbae-6d9240cb9191))
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(net 7 "Net-(J1-Pin_7)") (pinfunction "Pin_7") (pintype "passive") (tstamp 45b95870-b0e6-4dd9-866f-54ae89e39095))
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(footprint "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" (layer "B.Cu")
(tstamp 9edf844d-8917-4541-b84e-29685746fe80)
(at 63.5 72.325 -90)
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(tags "SOIC SO")
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SOIC_test.kicad_pro
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SOIC_test.kicad_sch
Unescape View File

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