commit 795d1610f182936de09cacc64840da6b43e4c3ed Author: cinnaboot Date: Tue Sep 19 12:40:24 2023 -0400 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a070cb5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,33 @@ +*-backups +gerbers/ +gcode/ + +# imported from gitea project kicad gitignore +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.sch-bak +*.kicad_prl +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache +*.lck + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/SOIC_test.kicad_pcb b/SOIC_test.kicad_pcb new file mode 100644 index 0000000..7664f55 --- /dev/null +++ b/SOIC_test.kicad_pcb @@ -0,0 +1,382 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (aux_axis_origin 45.72 88.9) + (pcbplotparams + (layerselection 0x0001020_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "Net-(J1-Pin_1)") + (net 2 "Net-(J1-Pin_2)") + (net 3 "Net-(J1-Pin_3)") + (net 4 "Net-(J1-Pin_4)") + (net 5 "Net-(J1-Pin_5)") + (net 6 "Net-(J1-Pin_6)") + (net 7 "Net-(J1-Pin_7)") + (net 8 "Net-(J2-Pin_1)") + (net 9 "Net-(J2-Pin_2)") + (net 10 "Net-(J2-Pin_3)") + (net 11 "Net-(J2-Pin_4)") + (net 12 "Net-(J2-Pin_5)") + (net 13 "Net-(J2-Pin_6)") + (net 14 "Net-(J2-Pin_7)") + + (footprint "Connector_PinHeader_2.54mm:PinHeader_1x07_P2.54mm_Vertical" (layer "F.Cu") + (tstamp a186ac2b-c801-4207-8722-e9dad9dc4df6) + (at 55.88 78.74 90) + (descr "Through hole straight pin header, 1x07, 2.54mm pitch, single row") + (tags "Through hole pin header THT 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