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VCO_AS3340: finish schematic, initial pcb work

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cinnaboot 3 years ago
parent
commit
2d535ac8f9
  1. 17698
      VCO_AS3340/VCO_AS3340.kicad_pcb
  2. 27
      VCO_AS3340/VCO_AS3340.kicad_pro
  3. 625
      VCO_AS3340/VCO_AS3340.kicad_sch

17698
VCO_AS3340/VCO_AS3340.kicad_pcb

File diff suppressed because it is too large Load Diff

27
VCO_AS3340/VCO_AS3340.kicad_pro

@ -48,7 +48,13 @@
"min_clearance": 0.5 "min_clearance": 0.5
} }
}, },
"diff_pair_dimensions": [], "diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [], "drc_exclusions": [],
"meta": { "meta": {
"version": 2 "version": 2
@ -165,8 +171,15 @@
"td_width_to_size_filter_ratio": 0.9 "td_width_to_size_filter_ratio": 0.9
} }
], ],
"track_widths": [], "track_widths": [
"via_dimensions": [], 0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false "zones_allow_external_fillets": false
}, },
"layer_presets": [], "layer_presets": [],
@ -399,7 +412,7 @@
"classes": [ "classes": [
{ {
"bus_width": 12, "bus_width": 12,
"clearance": 0.2, "clearance": 0.5,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
@ -409,9 +422,9 @@
"name": "Default", "name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25, "track_width": 0.5,
"via_diameter": 0.8, "via_diameter": 1.4,
"via_drill": 0.4, "via_drill": 0.8,
"wire_width": 6 "wire_width": 6
} }
], ],

625
VCO_AS3340/VCO_AS3340.kicad_sch

File diff suppressed because it is too large Load Diff
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