From b936a94428736ea4850c20fa4fa756d5f7d3cf05 Mon Sep 17 00:00:00 2001 From: cinnaboot Date: Sat, 10 Oct 2026 12:37:33 -0400 Subject: [PATCH] update midi_to_cv drafts --- content/midi_to_cv_part_1.md | 6 ++---- content/midi_to_cv_part_2.md | 1 + 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/content/midi_to_cv_part_1.md b/content/midi_to_cv_part_1.md index 43011e3..233b37f 100644 --- a/content/midi_to_cv_part_1.md +++ b/content/midi_to_cv_part_1.md @@ -25,14 +25,12 @@ For this project, I'm using the [le-potato](https://libre.computer/products/aml- [![Photo](images/brd_thumb.png)](images/brd.png) -For the [prototype](https://bxxa.cc/gitea/cinnaboot/synth-modules/src/branch/main/midi_to_cv), we're using a single [MCP4921](https://ww1.microchip.com/downloads/en/DeviceDoc/21897a.pdf) digital to analog converter (DAC) and an op-amp circuit to level shift the gate signals from the boards 3.3V digital IO to the expected 0-5V gate on/off. The MCP4921 is a 12-bit DAC, which means we have 4096 discrete steps at the output. +For the [prototype](https://bxxa.cc/gitea/cinnaboot/synth-modules/src/branch/main/midi_to_cv), we're using a single [MCP4921](https://ww1.microchip.com/downloads/en/DeviceDoc/21897a.pdf) digital to analog converter (DAC) and an op-amp circuit to level shift the gate signal from the board's 3.3V digital IO to the expected 0-5V gate on/off. The MCP4921 is a 12-bit DAC, which means we have 4096 discrete steps at the output. If we set the DAC reference voltage to ~5.018V, we can get a DAC output of 5V with a digital input value of 4080. This is cleanly divisilbe by `(5 * 12) = 60`, 5 octaves at 1V/octave. It's also divisible by `(10 * 12) = 120`, 10 octaves at 0.5V/octave, which can then be easily level shifted to 0-10V, or -5V-+5V. The prototype uses 0-10V, but -5V-+5V is probably the better option since those are the same levels as the audio signal levels already being passed around (at least now that we learned 10V p-p != -10V - +10V :) ). -The current plan is to add dedicated [sample and hold](https://en.wikipedia.org/wiki/Sample_and_hold) and level shifting ICs for 5 CV/Gate channels in the final module. +The current plan is to add dedicated [sample and hold](https://en.wikipedia.org/wiki/Sample_and_hold) and level shifting ICs for 5 CV/Gate channels in the final module. The DAC settling time is supposedly around 4.5 microseconds, according to the datasheet, which seems fast enough for 5 channels: `4.5 * 5 = 22.5us` per channel, and a quarter note at 200BPM is: `1 / (200 * 60 * 4) ~= 20us`. That's plenty fast for more reasonable tempos, but another limitation could be the output slew rate of the DAC at 0.55 V/us, and the unknowns from the sample hold and level shifting circuits. [![Photo](images/midi_to_cv_schematic_thumb.png)](images/midi_to_cv_schematic.png) -talk about choice of DAC, why not I2S? song tempo DPM * shortest note, DAC settling time, need for 5 channels, ldto overlay selection - - 5V input goes through polyfuse/input protection - 40pin header height - removing ground-digital ground resistor/grounding error for DAC ref diff --git a/content/midi_to_cv_part_2.md b/content/midi_to_cv_part_2.md index fbba41c..aa12681 100644 --- a/content/midi_to_cv_part_2.md +++ b/content/midi_to_cv_part_2.md @@ -5,6 +5,7 @@ Tags: Electronics, Hardware Status: draft - software: (separate post?) + - ldto overlay selection for i2c and spi - auto run on boot - notification led when ready - poll for usb midi controller?